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19-2084; Rev 0; 7/01
Tracking/Sequencing Triple/Quintuple Power-Supply Controllers
General Description
The MAX1964/MAX1965 power-supply controllers are designed to address cost-sensitive applications demanding voltage sequencing/tracking, such as cable modem consumer premise equipment (CPE), xDSL CPE, and set-top boxes. Operating off a low-cost, unregulated DC supply (such as a wall adapter output), the MAX1964 generates three positive outputs and the MAX1965 generates four positive outputs and one negative output to provide an inexpensive system power supply. The MAX1964 includes a current-mode synchronous step-down controller and two positive regulator gain blocks. The MAX1965 has one additional positive gain block and one negative regulator gain block. The main synchronous step-down controller generates a highcurrent output that is preset to 3.3V or adjustable from 1.236V to 0.75 VIN with an external resistive-divider. The 200kHz operating frequency allows the use of lowcost aluminum-electrolytic capacitors and low-cost power magnetics. Additionally, the MAX1964/MAX1965 step-down controllers sense the voltage across the lowside MOSFET's on-resistance to efficiently provide the current-limit signal, eliminating the need for costly current-sense resistors. The MAX1964/MAX1965 generate additional supply rails at low cost. The positive regulator gain blocks use an external PNP pass transistor to generate low voltage rails directly from the main step-down converter (such as 2.5V or 1.8V from the main 3.3V output) or higher voltages using coupled windings from the step-down converter (such as 5V, 12V, or 15V). The MAX1965's negative gain block uses an external NPN pass transistor in conjunction with a coupled winding to generate -5V, -12V, or -15V. All output voltages are externally adjustable, providing maximum flexibility. During startup, the MAX1964 features voltage sequencing and the MAX1965 features voltage tracking. Both controllers provide a powergood output that monitors all of the output voltages. o 4.5V to 28V Input Voltage Range o Master DC-DC Step-Down Converter: Preset 3.3V or Adjustable (1.236V to 0.75 x VIN) Output Voltage Fixed Frequency (200kHz) PWM Controller No Current-Sense Resistor Adjustable Current Limit 95% Efficient Soft-Start o Two (MAX1964)/Four (MAX1965) Analog Gain Blocks: Positive Analog Blocks Drive Low-Cost PNP Pass Transistors to Build Positive Linear Regulators Negative Analog Block (MAX1965) Drives a Low-Cost NPN Pass Transistor to Build a Negative Linear Regulator o Power-Good Indicator o Voltage Sequencing (MAX1964) or Tracking (MAX1965)
Features
MAX1964/MAX1965
Ordering Information
PART MAX1964TEEE MAX1965TEEP TEMP. RANGE -40C to +85C -40C to +85C PINPACKAGE 16 QSOP 20 QSOP fOSC (kHz) 200 200
Pin Configurations
TOP VIEW
POK 1 COMP 2 OUT 3
16 IN 15 VL 14 BST
POK COMP OUT FB B2 FB2 B3 FB3
1 2 3 4 5 6 7 8
20 IN 19 VL 18 BST 17 DH
Applications
xDSL, Cable, and ISDN Modems Set-Top Boxes Wireless Local Loop
FB 4 B2 5 FB2 6 B3 7 FB3 8
MAX1964
13 DH 12 LX 11 DL 10 GND 9 ILIM
MAX1965
16 LX 15 DL 14 GND 13 ILIM 12 FB5 11 B5
16-Pin QSOP
B4 9 FB4 10
Typical Operating Circuit appears at end of data sheet.
20-Pin QSOP
________________________________________________________________ Maxim Integrated Products
1
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
ABSOLUTE MAXIMUM RATINGS
IN, B2, B3, B4 to GND............................................-0.3V to +30V B5 to OUT...............................................................-20V to +0.3V VL, POK, FB, FB2, FB3, FB4, FB5 to GND ...............-0.3V to +6V LX to BST..................................................................-6V to +0.3V BST to GND ............................................................-0.3V to +36V DH to LX ....................................................-0.3V to (VBST + 0.3V) DL, OUT, COMP, ILIM to GND......................-0.3V to (VL + 0.3V) VL Output Current ...............................................................50mA VL Short Circuit to GND.................................................. 100ms Continuous Power Dissipation (TA = +70C) 16-Pin QSOP (derate 8.3mW/C above +70C)...........666mW 20-Pin QSOP (derate 9.1mW/C above +70C)...........727mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 12V, ILIM = FB = GND, VBST - VLX = 5V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER GENERAL Operating Input Voltage Range (Note 1) VIN VFB = 0, VOUT = 4V, VFB2 = VFB3 = VFB4 = 1.5V, VFB5 = -0.1V MAX1964 MAX1965 4.5 1.25 1.5 28 2.5 mA 3.0 V SYMBOL CONDITIONS MIN TYP MAX UNITS
Quiescent Supply Current VL REGULATOR Output Voltage Line Regulation Undervoltage Lockout Trip Level Minimum Bypass Capacitance DC-DC CONTROLLER Output Voltage (Preset Mode) Typical Output Voltage Range (Adjustable Mode) (Note 2) FB Set Voltage (Adjustable Mode) FB Dual-ModeTM Threshold FB Input Leakage Current FB to COMP Transconductance Current-Sense Amplifier Voltage Gain Current-Limit Threshold (Internal Mode) Current-Limit Threshold (External Mode) Switching Frequency
IIN
VL VUVLO CBYP(MIN) VOUT VOUT VSET
6V < VIN < 28V, 0.1mA < ILOAD <20mA VIN = 6V to 28V VL rising, 3% hysteresis (typ) 10m < ESR < 500m FB = GND
4.75 3.2
5.00 3.5 1
5.25 3.0 3.8
V % V F
3.272 VSET
3.34
3.355 0.75 VIN
V V V mV nA S V/V mV mV kHz
FB = COMP
1.221 50
1.236 100 0.01 100 4.9 250 530 200
1.252 150 100 140 5.44 310 620 240
IFB gm ALIM VVALLEY VVALLEY fOSC
VFB = 1.5V FB = COMP, ICOMP = 5A VIN - VLX = 250mV VILIM = 5.0V VILIM = 2.5V 70 4.46 190 440 160
Dual Mode is a trademark of Maxim Integrated Products, Inc. 2 _______________________________________________________________________________________
Tracking/Sequencing Triple/Quintuple Power-Supply Controllers
ELECTRICAL CHARACTERISTICS
(VIN = 12V, ILIM = FB = GND, VBST - VLX = 5V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER Maximum Duty Cycle Soft-Start Period Soft-Start Step Size FB Power-Up Sequence Threshold DH Output Low Voltage DH Output High Voltage DL Output Low Voltage DL Output High Voltage DH On-Resistance DL On-Resistance Output Drive Current LX, BST Leakage Current POSITIVE ANALOG GAIN BLOCKS FB2, FB3, FB4 Regulation Voltage FB2 Power-Up Sequence Threshold FB2, FB3, FB4 to B_ Transconductance Error Feedback Input Leakage Current Driver Sink Current NEGATIVE ANALOG GAIN BLOCK FB5 Regulation Voltage FB5 to B5 Transconductance Error Feedback Input Leakage Current Driver Source Current POWER GOOD (POK) OUT Trip Level (Preset Mode) FB Trip Level (Adjustable Mode) FB2, FB3, FB4 Trip Level FB5 Trip Level POK Output Low Level POK Output High Leakage FB = GND, falling edge, 3% hysteresis (typ) Falling edge, 3% hysteresis (typ) Falling edge, 3% hysteresis (typ) Rising edge, 35mV hysteresis (typ) ISINK = 1mA VPOK = 5V 2.88 1.070 1.070 368 3.0 1.114 1.114 530 3.12 1.159 1.159 632 0.4 1 V V V mV V A VFB5 IFB5 IB5 VB5 = VOUT - 2V, VOUT = 3.5V, IB5 = 1mA (source) VB5 = 0, IB5 = 0.5mA to 5mA (source) VFB5 = -100mV VFB5 = 200mV, VB5 = VOUT - 2.0V, VOUT = 3.5V 10 -20 -5 -13 0.01 25 +10 -20 100 mV mV nA mA VFB_ IFB_ IB_ VB2 = VB3 = VB4 = 5V, IB2 = IB3 = IB4 = 1mA (sink) MAX1964, FB2 rising, B3 turns on VB2 = VB3 = VB4 = 5V, IB2 = IB3 = IB4 = 0.5mA to 5mA (sink) VFB2 = VFB3 = VFB4 = 1.5V VFB2 = VFB3 = VFB4 = 1.188V VB2 = VB3 = VB4 = 2.5V VB2 = VB3 = VB4 = 4.0V 10 1.226 1.24 1.145 13 0.01 21 24 22 100 1.257 V V mV nA mA MAX1964, FB rising, B2 turns on ISINK = 10mA, measured from DH to LX ISOURCE = 10mA, measured from BST to DH ISINK = 10mA, measured from DL to GND ISOURCE = 10mA, measured from DL to GND High (DH to BST) and low (DH to LX) High (DL to VL) Low (DL to GND) Sourcing or sinking, VDH or VDL = VL/2 VBST = VLX = VIN = 28V, VFB = 1.5V VL - 0.1 1.5 4.3 0.7 0.5 0.04 10 4 10 2 40 20 SYMBOL DMAX tSOFT CONDITIONS MIN 77 TYP 82 1024 VREF/64 1.145 40 MAX 90 UNITS % 1/fOSC V V mV mV mV V A A
MAX1964/MAX1965
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, ILIM = FB = GND, VBST - VLX = 5V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER Thermal Shutdown Thermal Shutdown Hysteresis SYMBOL CONDITIONS Rising temperature MIN TYP 160 15 MAX UNITS C C
THERMAL PROTECTION (NOTE 3)
ELECTRICAL CHARACTERISTICS
(VIN = 12V, ILIM = FB = GND, VBST - VLX = 5V, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER GENERAL Operating Input Voltage Range (Note 1) VIN VFB = 0, VOUT = 4V, VFB2 = VFB3 = VFB4 = 1.5V, VFB5 = -0.1V MAX1964 MAX1965 4.5 28 2.5 mA 3.0 V SYMBOL CONDITIONS MIN TYP MAX UNITS
Quiescent Supply Current
IIN
VL REGULATOR Output Voltage Line Regulation Undervoltage Lockout Trip Level DC-DC CONTROLLER Output Voltage (Preset Mode) Feedback Set Voltage (Adjustable Mode) Current-Sense Amplifier Voltage Gain Current-Limit Threshold (Internal Mode) Current-Limit Threshold (External Mode) Switching Frequency Maximum Duty Cycle POSITIVE ANALOG GAIN BLOCKS FB2, FB3, FB4 Regulation Voltage FB2, FB3, FB4 to B_ Transconductance Error VFB_ VB2 = VB3 = VB4 = 5V, IB2 = IB3 = IB4 = 1mA (sink) VB2 = VB3 = VB4 = 5V, IB2 = IB3 = IB4 = 0.5mA to 5mA (sink) 1.215 1.265 28 V mV VOUT VSET ALIM VVALLEY VVALLEY fOSC DMAX FB = GND FB = COMP VIN - VLX = 250mV VILIM = 5.0V VILIM = 2.5V 3.247 1.211 4.12 150 400 160 74 3.38 1.261 5.68 350 660 240 90 V V V/V mV mV kHz % VUVLO VL 6V < VIN < 28V, 0.1mA < ILOAD <20mA VIN = 6V to 28V VL rising, 3% hysteresis (typ) 3.0 4.75 5.25 3.0 4.0 V % V
4
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 12V, ILIM = FB = GND, VBST - VLX = 5V, TA = -40C to +85C, unless otherwise noted.) (Note 4)
PARAMETER SYMBOL CONDITIONS VB5 = VOUT - 2V, VOUT = 3.5V, IB5 = 1mA (source) VFB5 VB5 = 0, IB5 = 0.5mA to 5mA (source) FB = GND, falling edge, 3% hysteresis (typ) Falling edge, 3% hysteresis (typ) Falling edge, 3% hysteresis (typ) Rising edge, 35mV hysteresis (typ) 2.85 1.058 1.058 325 MIN TYP MAX UNITS
MAX1964/MAX1965
NEGATIVE ANALOG GAIN BLOCK FB5 Regulation Voltage FB5 to B5 Transconductance Error POWER GOOD (POK) OUT Trip Level (Preset Mode) FB Trip Level (Adjustable Mode) FB2, FB3, FB4 Trip Level FB5 Trip Level 3.15 1.17 1.17 675 V V V mV -25 +10 -30 mV mV
Note 1: Note 2: Note 3: Note 4:
Connect VL to IN for operation with VIN < 5V. See Output Voltage Selection section. The internal 5V linear regulator (VL) powers the thermal shutdown block. Shorting VL to GND disables thermal shutdown. Specifications to -40C are guaranteed by design, not production tested.
Typical Operating Characteristics
(Circuit of Figure 1, VIN = 12V, VOUT = 3.3V, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT (PRESET MODE)
MAX1964/65 toc01
OUTPUT VOLTAGE vs. LOAD CURRENT (PRESET MODE)
MAX1964/65 toc02
EFFICIENCY vs. LOAD CURRENT (ADJUSTABLE MODE)
VIN = 6.5V 90 EFFICIENCY (%) VIN = 8V VIN = 12V 70 VIN = 18V VIN = 24V VOUT = +5.0V
MAX1964/65 toc03
100 VIN = 6.5V 90 EFFICIENCY (%)
3.33 3.32 OUTPUT VOLTAGE (V) 3.31 3.30 3.29 3.28
100
80 VIN = 8V 70 VIN = 12V VIN = 18V 60 VIN = 24V VOUT = 3.3V 50 0.01 0.1 1 10 LOAD CURRENT (A)
80
60
3.27 0 0.5 1.0 1.5 2.0 2.5 3.0 LOAD CURRENT (A)
50 0.01 0.1 1 10 LOAD CURRENT (A)
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VOUT = 3.3V, TA = +25C, unless otherwise noted.)
OUPUT VOLTAGE vs. LOAD CURRENT (ADJUSTABLE MODE)
MAX1964/65 toc04
INTERNAL 5V LINEAR REGULATOR vs. LOAD CURRENT
MAX1964/65 toc05
LOAD TRANSIENT (STEP-DOWN CONVERTER)
MAX1964/65 toc06
5.05
5.05
5.03 OUTPUT VOLTAGE (V)
5.03
5.0V VL (V) 5.01 5.01
A
4.99
4.99
1A B 0
4.97
4.97
4.95 0 0.5 1.0 LOAD CURRENT (A) 1.5 2.0
4.95 0 5 10 15 20 25 30 40s/div A. VOUT = 5V, 100mV/div B. IOUT = 10mA TO 1A, 500mA/div VIN = 12V LOAD CURRENT (mA)
SWITCHING WAVEFORMS (STEP-DOWN CONVERTER)
MAX1964/65 toc07
SOFT-START (STEP-DOWN CONVERTER)
MAX1964/65 toc08
MAX1964 STARTUP WAVEFORM (VOLTAGE SEQUENCING)
MAX1964/65 toc09
5.00V 4.95V 12V B 0 A
5V 0 5V
A
5V 1.8V
A
B B 3.3V 0 C 1A C 0 C D
1A 0.5A
40s/div A. VOUT = 5.0V, 50mV/div B. VLX,10V/div C. INDUCTOR CURRENT, 500mA/div VIN = 12V, ROUT1 = 5V
1ms/div A. VL = 5V, 5V/div B. VOUT1 = 5V (ADJ),2V/div C. INDUCTOR CURRENT, 1A/div VIN = STEPPED FROM 0 TO 12V, ROUT1 = 10
200s/div A. VOUT1 = 5V (ADJ), 2V/div B. VOUT2 = 1.8V, 1V/div C. VOUT3 = 3.3V, 2V/div D. VPOK, 5V/div VIN = STEPPED FROM 0 TO 12V, ROUT1 = 5
6
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VOUT = 3.3V, TA = +25C, unless otherwise noted.)
POSITIVE LINEAR REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT (QLDO = 2N3905)
MAX1964/65 toc12
MAX1964/MAX1965
MAX1965 STARTUP WAVEFORM (VOLTAGE TRACKING)
MAX1964/65 toc10
POSITIVE LINEAR REGULATOR BASEDRIVE CURRENT vs. BASE-DRIVE VOLTAGE
A BASE-DRIVE SINK CURRENT (mA) 35 30 25 20 15 10 5 0 0 2 4 B2, B3 AND B4 (MAX1965) ONLY 6 8 10 VFB_ = 0.96VREF VFB_ = 1.0V
MAX1964/65 toc11
40 B C D
2.50
4V 2V 0 -2V -4V
2.48 OUTPUT VOLTAGE (V) VSUP(POS) = 5.0V 2.46 VSUP(POS) = 3.3V 2.44
E 5V F 0 400s/div A. VOUT4 = 5.0V, 2V/div D. VOUT3 = 1.8V/div E. VOUT5 = -5.0V, 2V/div B. VOUT1 = 3.3V, 2V/div F. VPOK, 5V/div C. VOUT2 = 2.5V, 2V/div VIN = STEPPED FROM 0 TO 12V, ROUT1 = 6.6 CIRCUIT OF FIGURE 6
2.42 0.01 0.1 1 10 100 1000 LOAD CURRENT (mA)
BASE VOLTAGE (V)
POSITIVE LINEAR REGULATOR OUTPUT VOLTAGE vs. SUPPLY VOLTAGE (QLDO = 2N3905)
MAX1964/65 toc13
POSITIVE LINEAR REGULATOR POWER-SUPPLY REJECTION RATIO (QLDO = 2N3905)
MAX1964/65 toc14
POSITIVE LINEAR REGULATOR LOAD TRANSIENT (QLDO = 2N3905)
100mA
2.50
80 70 60 PSRR (dB) 50 40 30
MAX1964/65 toc15
OUTPUT VOLTAGE (V)
2.48 IOUT2 = 1mA 2.46 IOUT2 = 100mA
A 0
2.467V B
2.44
20 10 IOUT2 = 50mA 2.457V
2.42 2 3 4 5 6 7 8 SUPPLY VOLTAGE (V)
0 0.1 1 10 FREQUENCY (kHz) 100 1000 10s/div A. IOUTZ = 1mA TO 100mA, 50mA/div B. VOUTZ = 2.5V, 5mV/div CLDO(POS) = 10F CERAMIC, VSUP(POS) = 3.3V CIRCUIT OF FIGURE 1
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VOUT = 3.3V, TA = +25C, unless otherwise noted.)
MAX1964/65 toc16
MAX1964/65 toc17
70 60 PSRR (dB) 50 40 30
OUTPUT VOLTAGE (V)
2.46
OUTPUT VOLTAGE (V)
2.48
VSUP(POS) = 5.0V
2.48
IOUT2 = 1mA
VSUP(POS) = 3.3V
2.46
IOUT2 = 100mA
2.44
2.44
20 10 IOUT2 = 150mA
2.42 0.01 0.1 1 10 100 1000 LOAD CURRENT (mA)
2.42 2 4 6 8 10 12 SUPPLY VOLTAGE (V)
0 0.1 1 10 FREQUENCY (kHz) 100 1000
POSITIVE LINEAR REGULATOR LOAD TRANSIENT (QLDO = TIP30)
250mA 0
NEGATIVE LINEAR REGULATOR BASEDRIVE CURRENT vs. BASE-DRIVE VOLTAGE
BASE-DRIVE SOURCE CURRENT (mA) 40 35 30 25 20 15 10 5 0 0 2 4 VOUT = 5.0V VOUT = 3.3V B5 (MAX1965) ONLY 6 8 10 VFB5 = 50mV VFB5 = 250mV
MAX1964/65 toc20
NEGATIVE LINEAR REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT (QLDO = TIP29)
VSUP(NEG) = -15V VOUT3 = 5V OUTPUT VOLTAGE (V) -12.06
MAX1964/65 toc21
MAX1964/65 toc19
45
-12.00
A
-12.12
2.473V B 2.453V
-12.18
-12.24 0.01 0.1 VOUT - VB5 (V) 1 100 10 LOAD CURRENT (mA) 1000
10s A. IOUT2 = 10mA TO 250mA, 200mA/div B. VOUT2 = 2.5V, 10mV/div CLDO(POS) = 10F CERAMIC, VSUP(POS) = 3.3V CIRCUIT OF FIGURE 1
8
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MAX1964/65 toc18
2.50
POSITIVE LINEAR REGUALTOR OUTPUT VOLTAGE vs. LOAD CURRENT (QLDO = TIP30)
2.50
POSITIVE LINEAR REGULATOR OUTPUT VOLTAGE vs. SUPPLY VOLTAGE (QLDO = TIP30)
80
POSITIVE LINEAR REGULATOR POWER-SUPPLY REJECTION RATIO (QLDO = TIP30)
Tracking/Sequencing Triple/Quintuple Power-Supply Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, VOUT - 3.3V, TA = +25C, unless otherwise noted.)
NEGATIVE LINEAR REGULATOR OUTPUT VOLTAGE vs. SUPPLY VOLTAGE (QLDO = TIP29)
MAX1964/65 toc22
MAX1964/MAX1965
-12.00
OUTPUT VOLTAGE (V)
-12.06
-12.12 ILDO(NEG) = 100mA -12.18 ILDO(NEG) = 1mA -12.24 -20 -18 -16 -14 -12 -10 SUPPLY VOLTAGE (V)
Pin Description
PIN MAX1964 1 MAX1965 1 NAME FUNCTION Open-Drain Power-Good Output. POK is low when any output voltage is more than 10% below its regulation point. POK is high impedance when all the outputs are in regulation. Connect a resistor between POK and VL for logic-level voltages. Compensation Pin. Connect the compensation network to GND to compensate the control loop. Regulated Output Voltage High-Impedance Sense Input. Internally connected to a resistive-divider and negative gain block (MAX1965). Dual-Mode Switching-Regulator Feedback Input. Connect to GND for the preset 3.3V output. Connect to a resistive-divider from the output to FB to GND to adjust the output voltage between 1.236V and 0.75 VIN. The feedback set point is 1.236V. Open-Drain Output PNP Transistor Driver (Regulator 2). Internally connected to the drain of a DMOS. B2 connects to the base of an external PNP pass transistor to form a positive linear regulator. Analog Gain Block Feedback Input (Regulator 2). Connect to a resistive-divider between the positive linear regulator's output and GND to adjust the output voltage. The feedback set point is 1.24V.
POK
2 3
2 3
COMP OUT
4
4
FB
5
5
B2
6
6
FB2
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
Pin Description (continued)
PIN MAX1964 7 MAX1965 7 NAME FUNCTION Open-Drain Output PNP Transistor Driver (Regulator 3). Internally connected to the drain of a DMOS. B3 connects to the base of an external PNP pass transistor to form a positive linear regulator. Analog Gain Block Feedback Input (Regulator 3). Connect to a resistive-divider between the positive linear regulator's output and GND to adjust the output voltage. The feedback set point is 1.24V. Open-Drain Output PNP Transistor Driver (Regulator 4). Internally connected to the drain of a DMOS. B4 connects to the base of an external PNP pass transistor to form a positive linear regulator. Analog Gain Block Feedback Input (Regulator 4). Connect to a resistive-divider between the positive linear regulator's output and GND to adjust the output voltage. The feedback set point is 1.24V. Open-Drain Output NPN Transistor Driver (Regulator 5). Internally connected to the drain of a P-channel MOSFET. B5 connects to the base of an external NPN pass transistor to form a negative linear regulator. Analog Gain Block Feedback Input (Regulator 5). Connect to a resistive-divider between the negative linear regulator's output and a positive reference voltage, typically one of the positive linear regulator outputs, to adjust the output voltage. The feedback set point is at GND. Dual-Mode Current-Limit Adjustment Input. Connect to VL for the default 250mV current-limit threshold. In adjustable mode, the current-limit threshold voltage is 1/5 th the voltage present at ILIM. Connect to a resistive-divider between VL and GND to adjust VILIM between 500mV and 2.5V. The logic threshold for switchover to the 250mV default value is approximately VL - 1V. Ground Low-Side Gate-Driver Output. DL swings between GND and VL. Inductor Connection. Used for current-sense between IN and LX, and used for currentlimit between LX and GND. High-Side Gate-Driver Output. DH swings between LX and BST. Boost Flying Capacitor Connection. Connect BST to the external boost diode and capacitor as shown in the Standard Application Circuit. Internal 5V Linear Regulator Output. Supplies the IC and powers the DL low-side gate driver and external boost diode and capacitor. Bypass with a 1F or greater ceramic capacitor to GND. Input Supply Voltage. 4.5V to 28V. Bypass to GND with a 1F or greater ceramic capacitor close to the IC.
B3
8
8
FB3
--
9
B4
--
10
FB4
--
11
B5
--
12
FB5
9
13
ILIM
10 11 12 13 14
14 15 16 17 18
GND DL LX DH BST
15
19
VL
16
20
IN
10
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
D1 CENTRAL CMPSH-3 INPUT 9V TO 18V CIN 470F
IN C1 1F
BST DH
RGATE(NH) 10 NH CBST 0.1F RGATE(NL) 10
INTERNATIONAL RECTIFIER IRF7101
VL C2 1F ILIM RPOK 100k
LX
VOUT1 5V AT 1A COUT 1000F R1 30k
L1 33H NL
DL
MAX1964
OUT FB R2 10k
TO LOGIC
POK
GND
CBE2 2200pF RBE2 220 R3 4.64k R4 10k
C3 1F
B2 RCOMP 5M COMP CCOMP1 470pF CCOMP2 47pF FB2
Q1 TIP30
VOUT2 1.8V AT 300mA C4 10F
CBE3 1000pF RBE3 220 R5 4.99k R4 3.0k
C5 1F
B3
Q2 TIP32
VOUT3 3.3V AT 750mA C6 10F POWER GROUND
FB3
COUT : 1000F, 10V SANYO (CZ SERIES)
ANALOG GROUND
Figure 1. MAX1964 Standard Application Circuit
Detailed Description
The MAX1964/MAX1965 power-supply controllers provide system power for cable and xDSL modems. The main step-down DC-DC controller operates in a current-mode pulse-width-modulation (PWM) control scheme to ease compensation requirements and provide excellent load and line transient response.
The MAX1964 includes two analog gain blocks to regulate two additional positive auxiliary output voltages, and the MAX1965 includes four analog gain blocks to regulate three additional positive and one negative auxiliary output voltages. The positive regulator gain blocks can be used to generate low voltage rails directly from the main step-down converter or higher voltages using coupled windings from the step-down converter. The
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
negative gain block can be used in conjunction with a coupled winding to generate -5V, -12V, or -15V.
DC-DC Controller
The MAX1964/MAX1965 step-down converters use a pulse-width-modulated (PWM) current-mode control scheme (Figure 2). An internal transconductance amplifier establishes an integrated error voltage at the COMP pin. The heart of the current-mode PWM controller is an open-loop comparator that compares the integrated voltage-feedback signal against the amplified currentsense signal plus the slope compensation ramp. At each rising edge of the internal clock, the high-side MOSFET turns on until the PWM comparator trips or the maximum duty cycle is reached. During this on-time, current ramps up through the inductor, sourcing current to the output and storing energy in a magnetic field. The current-mode feedback system regulates the peak inductor current as a function of the output voltage error signal. Since the average inductor current is nearly the same as the peak inductor current (assuming that the inductor value is relatively high to minimize ripple current), the circuit acts as a switch-mode transconductance amplifier. It pushes the output LC filter pole, normally found in a voltage-mode PWM, to a higher frequency. To preserve inner-loop stability and eliminate inductor stair casing, a slope-compensation ramp is summed into the main PWM comparator. During the second-half of the cycle, the high-side MOSFET turns off and the low-side N-Channel MOSFET turns on. Now the inductor releases the stored energy as its current ramps down, providing current to the output. Therefore, the output capacitor stores charge when the inductor current exceeds the load current, and discharges when the inductor current is lower, smoothing the voltage across the load. Under overload conditions when the inductor current exceeds the selected current-limit (see the Current Limit section), the high-side MOSFET is not turned on at the rising edge of the clock and the low-side MOSFET remains on to let the inductor current ramp down. The MAX1964/MAX1965 operate in a forced-PWM mode, so even under light loads, the controller maintains a constant switching frequency to minimize crossregulation errors in applications that use a transformer. So the low-side gate-drive waveform is the complement of the high-side gate-drive waveform, which causes the inductor current to reverse under light loads. Current-Sense Amplifier The one MAX1964/MAX1965's one current-sense circuit amplifies (A V = 4.9) the current-sense voltage generated by the high-side MOSFET's on resistance
12
(RDS(ON) IINDUCTOR). This amplified current-sense signal and the internal slope compensation signal are summed together (VSUM) and fed into the PWM comparator's inverting input. The PWM comparator turns off the high-side MOSFET when the VSUM exceeds the integrated feedback voltage (VCOMP). Place the highside MOSFET no further than 5mm from the controller and connect IN and LX to the MOSFET using Kelvin sense connections to guarantee current-sense accuracy and improve stability. Current-Limit Circuit The current-limit circuit employs a unique "valley" current-limiting algorithm that uses the low-side MOSFET's on-resistance as a sensing element (Figure 3). If the voltage across the low-side MOSFET (R DS(ON) IINDUCTOR) exceeds the current-limit threshold at the beginning of a new oscillator cycle, the MAX1964/ MAX1965 will not turn on the high-side MOSFET. The actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the lowside MOSFET on-resistance, inductor value, input voltage, and output voltage. The reward for this uncertainty is robust, lossless overcurrent limiting. In adjustable mode, the current-limit threshold voltage is approximately one-fifth the voltage seen at ILIM (IVALLEY = 0.2 VILIM). Adjust the current-limit threshold by connecting a resistive-divider from VL to ILIM to GND. The current-limit threshold can be set from 106mV to 530mV, which corresponds to ILIM input voltages of 500mV to 2.5V. This adjustable current limit accommodates MOSFETs with a wide range of on-resistance characteristics (see the Design Procedure section). The current-limit threshold defaults to 250mV when ILIM is connected to VL. The logic threshold for switchover to the 250mV default value is approximately VL - 1V. Carefully observe the PC board layout guidelines to ensure that noise and DC errors don't corrupt the current-sense signals seen by LX and GND. The IC must be mounted close to the low-side MOSFET with short (less than 5mm), direct traces making a Kelvin sense connection. Synchronous Rectifier Driver (DL) Synchronous rectification reduces conduction losses in the rectifier by replacing the normal Schottky catch diode with a low-resistance MOSFET switch. The MAX1964/MAX1965 also use the synchronous rectifier to ensure proper startup of the boost gate-driver circuit and to provide the current-limit signal.
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
BIAS OK
MAX1964
VREF COMP OUT ENABLE 1.114V
THERMAL SHDN
3.5V FB IN SOFTSTART VREF 1.24V 100mV CLK BST SLOPE COMP
AV = 4.9
VL LDO 5V VL
DH 0.9VREF FB2 LX
B2 DL AV = 5
GND
100k 0.9VREF 400k ILIM
FB3
0.9VL 250mV B3 POK
0.9VREF
ENABLE
Figure 2a. MAX1964 Functional Diagram
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
BIAS OK
MAX1965
VREF COMP OUT ENABLE 1.114V
THERMAL SHDN
3.5V FB IN SOFTSTART VREF 1.24V 100mV CLK BST SLOPE COMP
AV = 4.9
VL LDO 5V VL
DH 0.9VREF FB_ LX
B_ DL AV = 5
GND
100k 0.9VREF 400k B5 ILIM OUT 0.9VL FB5 250mV POK
500mV
ENABLE
Figure 2b. MAX1965 Functional Diagram
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
-IPEAK
ILOAD INDUCTOR CURRENT
IVALLEY
IPEAK = IVALLEY +
[
(VIN - VOUT) VOUT VINOSC L
( )]
TIME
Figure 3. "Valley" Current-Limit Threshold Point
The DL low-side drive waveform is always the complement of the DH high-side drive waveform (with controlled dead time to prevent cross-conduction or "shoot-through"). A dead-time circuit monitors the DL output and prevents the high-side FET from turning on until DL is fully off. In order for the dead-time circuit to work properly, there must be a low-resistance, lowinductance path from the DL driver to the MOSFET gate. Otherwise, the sense circuitry in the MAX1964/ MAX1965 will interpret the MOSFET gate as "off" when gate charge actually remains. Use very short, wide traces (50mils to 100mils wide if the MOSFET is 1 inch from the device). The dead time at the other edge (DH turning off) is determined by a fixed internal delay. High-Side Gate-Drive Supply (BST) Gate-drive voltage for the high-side N-channel switch is generated by a flying-capacitor boost circuit (Figure 1). The capacitor between BST and LX is alternately charged from the VL supply and placed parallel to the high-side MOSFET's gate and source terminals. On startup, the synchronous rectifier (low-side MOSFET) forces LX to ground and charges the boost capacitor to 5V. On the second half-cycle, the switchmode power supply turns on the high-side MOSFET by closing an internal switch between BST and DH. This provides the necessary gate-to-source voltage to turn on the high-side switch, an action that boosts the 5V gate-drive signal above the input voltage.
(VL) with a ceramic capacitor of at least 1F to GND. The VIN-to-VL dropout voltage is typically 200mV, so when VIN is less than 5.2V, VL is typically VIN - 200mV. The internal linear regulator can source up to 20mA to supply the IC, power the low-side gate driver, charge the external boost capacitor, and supply small external loads. When driving particularly large FETs, little or no regulator current may be available for external loads. For example, when switched at 200kHz, a large FET with 40nC total gate charge requires 40nC x 200kHz, or 8mA.
Undervoltage Lockout
If VL drops below 3.5V, the MAX1964/MAX1965 assumes that the supply voltage is too low to make valid decisions, so the undervoltage lockout (UVLO) circuitry inhibits switching, forces POK low, and forces the DL and DH gate drivers low. After VL rises above 3.5V, the controller powers up the outputs (see Startup section).
Startup
Externally, the MAX1964/MAX1965 start switching when VL rises above the 3.5V undervoltage lockout threshold. However, the controller is not enabled unless all four conditions are met: 1) VL exceeds the 3.5V undervoltage lockout threshold, 2) the internal reference exceeds 92% of its nominal value (VREF > 1.145V), 3) the internal bias circuitry powers up, and 4) the thermal limit is not exceeded. Once the MAX1964/MAX1965 assert the internal enable signal, the step-down controller starts switching and enables soft-start. The soft-start circuitry gradually ramps up to the reference voltage in order to control the rate of rise of the step-down controller and reduce input surge currents
15
Internal 5V Linear Regulator (VL)
All MAX1964/MAX1965 functions, except the currentsense amplifier, are internally powered from the onchip, low-dropout 5V regulator. The maximum regulator input voltage (VIN) is 28V. Bypass the regulator's output
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
during startup. The soft-start period is 1024 clock cycles (1024/f OSC ), and the internal soft-start DAC ramps up the voltage in 64 steps. The output reaches regulation when soft-start is completed, regardless of output capacitance and load. Output Voltage Sequencing (MAX1964) After the reference powers up, the controller begins a startup sequence. First, the main DC-DC step-down converter powers up with soft-start enabled. Once the step-down converter reaches 92% of its nominal value (VFB > 1.145V) and soft-start is completed, the controller powers up the first positive linear regulator. Once the first linear regulator reaches 92% of its nominal value (VFB2 > 1.145V), the second linear regulator powers up. Once all three output voltages exceed 92% of their nominal values, the active-high ready signal (POK) goes high (see Power-Good Output section). Output Voltage Tracking (MAX1965) After the reference powers up, the controller simultaneously powers up all five output voltages. The main DCDC step-down converter powers up with soft-start enabled while the linear regulators are fully activated. However, the linear regulators' inputs are typically connected to or derived from the step-down converter output voltage. Since the linear regulators are fully active, the pass transistors immediately saturate, allowing these output voltages to track the step-down converter's slow rising output voltage (see Typical Operating Characteristics). Once all five output voltages exceed 92% of their nominal values, the active-high ready signal (POK) goes high (see Power-Good Output section). conditions. If the VL output is short-circuited, thermal overload protection is disabled. During a thermal event, the main step-down converter and the linear regulators are turned off, POK goes low, and soft-start is reset.
Design Procedure
DC-DC Step-Down Converter
Output Voltage Selection The step-down controller's feedback input features dual mode operation. Connect the output to OUT and connect FB to GND for the preset 3.3V output voltage. Alternatively, the MAX1964/MAX1965 output voltage may be adjusted by connecting a voltage-divider from the output to FB to GND (Figure 4). Select R2 in the 5k to 50k range. Calculate R1 with the following equation: V R1 = R2 OUT - 1 VSET where VSET = 1.236V and VOUT may range from 1.236V to approximately 0.75 VIN (up to 20V). If VOUT > 5.5V, connect OUT to GND (MAX1964) or to one of the positive linear regulators (MAX1965) with an output voltage between 2V and 5V. Inductor Value Three key inductor parameters must be specified: inductance value (L), peak current (IPEAK), and DC resistance (RDC). The following equation includes a constant LIR, which is the ratio of inductor peak-to-peak AC current to DC load current. A higher LIR value allows smaller inductance, but results in higher losses and higher output ripple. A good compromise between size and losses is a 30% ripple-current to load-current ratio (LIR = 0.3). The switching frequency, input voltage, output voltage, selected LIR determine the inductor value as follows: L= VOUT (VIN - VOUT )
Power-Good Output (POK)
POK is an open-drain output. The MOSFET turns on and pulls POK low when any output falls below 90% of its nominal regulation voltage. Once all of the outputs exceed 92% of their nominal regulation voltages and soft-start is completed, POK goes high impedance. To obtain a logic voltage output, connect a pullup resistor from POK to VL. A 100k resistor works well for most applications. If unused, leave POK grounded or unconnected.
VIN SW ILOAD(MAX)LIR
Thermal overload Protection
Thermal overload protection limits total power dissipation in the MAX1964/MAX1965. When the junction temperature exceeds TJ = +160C, a thermal sensor shuts down the device, forcing DL and DH low, allowing the IC to cool. The thermal sensor turns the part on again after the junction temperature cools by 15C, resulting in a pulsed output during continuous thermal overload
where fSW is 200kHz. The exact inductor value is not critical and can be adjusted in order to make trade-offs among size, cost, and efficiency. Lower inductor values minimize size and cost, but they also increase the output ripple and reduce the efficiency due to higher peak currents. On the other hand, higher inductor values increase efficiency, but at some point resistive losses due to extra turns of wire will exceed the benefit gained from lower AC current levels.
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
D1 INPUT 4.5V TO 28V
IN C1
MAX1964 MAX1965 BST
DH CBST NH L
CIN
OUTPUT 1.25V TO 5V* COUT
VL C2 ILIM RPOK POK RCOMP COMP CCOMP1 CCOMP2
LX NL
DL
OUT GND FB
R1
R2
* FOR OUTPUT VOLTAGES > 5V, SEE "OUTPUT VOLTAGE SELECTION."
Figure 4. Adjustable Output Voltage
Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The chosen inductor's saturation rating must exceed the peak inductor current: LIR IPEAK = ILOAD(MAX) + I 2 LOAD(MAX) Setting the Current Limit The minimum current-limit threshold must be high enough to support the maximum load current at the minimum tolerance level of the current-limit circuit. The valley of the inductor current occurs at I LOAD(MAX) minus half of the ripple current: VVALLEY(LOW) RDS(ON) LIR > ILOAD(MAX) - I 2 LOAD(MAX)
ture. A good general rule is to allow 0.5% additional resistance for each C of the MOSFET junction temperature rise. Connect ILIM to VL for the default 250mV (typ) currentlimit threshold. For an adjustable threshold, connect a resistive-divider from VL to ILIM to GND. The external adjustment range of 500mV to 2.5V corresponds to a current-limit threshold of 106mV to 530mV. When adjusting the current limit, use 1% tolerance resistors and a 10A divider current to prevent a significant increase in the current-limit tolerance. MOSFET Selection The MAX1964/MAX1965's step-down controller drives two external logic-level N-channel MOSFETs as the circuit switch elements. The key selection parameters are: 1. On-resistance (RDS(ON)) 2. Maximum drain-to-source voltage (VDS(MAX)) 3. Minimum threshold voltage (VTH(MIN)) 4. Total gate charge (Qg) 5. Reverse transfer capacitance (CRSS) The high-side N-channel MOSFET must be a logic-level type with guaranteed on-resistance specifications at VGS 4.5V. Select the high-side MOSFET's on-resistance (RDS(ON)) so IPEAK RDS(ON) 225mV for the
17
where R DS(ON) is the on-resistance of the low-side MOSFET (NL). For the MAX1964/MAX1965, the minimum current-limit threshold is 190mV (for the typical 250mV default setting). Use the worst-case maximum value for RDS(ON) from the MOSFET NL data sheet, and add some margin for the rise in RDS(ON) over tempera-
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
current-sense range. For a good compromise between efficiency and cost, choose a high-side MOSFET (NH) that has conduction losses equal to the switching losses at the optimum input voltage. Check to ensure that the conduction losses at minimum input voltage don't exceed the package thermal limits or violate the overall thermal budget. Check to ensure that the conduction losses plus switching losses at the maximum input voltage don't exceed package ratings or violate the overall thermal budget. The low-side MOSFET (NL) provides the current-limit signal, so choose a MOSFET with an RDS(ON) large enough to provide adequate circuit protection (see the Setting the Current-Limit section): V RDS(ON) = VALLEY IVALLEY Use the worst-case maximum value for RDS(ON) from the MOSFET NL data sheet, and add some margin for the rise in RDS(ON) over temperature. A good general rule is to allow 0.5% additional resistance for each C of the MOSFET junction temperature rise. Ensure that the MAX1964/MAX1965 DL gate drivers can drive NL; in other words, check that the dv/dt caused by NH turning on does not pull up the NL gate due to drain-to-gate capacitance, causing cross-conduction problems. MOSFET package power dissipation often becomes a dominant design factor. I2R power losses are the greatest heat contributor for both high-side and low-side MOSFETs. I2R losses are distributed between NH and NL according to duty factor as shown in the equations below. Generally, switching losses affect only the highside MOSFET, since the low-side MOSFET is a zerovoltage switched device when used in the buck topology. Gate-charge losses are dissipated by the driver and do not heat the MOSFET. Calculate the temperature rise according to package thermal-resistance specifications to ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature. The worst-case dissipation for the high-side MOSFET (PNH) occurs at both extremes of input voltage, and the worstcase dissipation for the low-side MOSFET (PNL) occurs at maximum input voltage. Q + QGD PNH(SWITCHING) = VINILOAD OSC GS IGATE IGATE is the average DH driver output current capability determined by:
18
IGATE =
2 RDS(ON)DH + RGATE
(
VL
)
where RDS(ON)DH is the high-side MOSFET driver's onresistance (4 max), and R GATE is any resistance placed between DH and the high-side MOSFET's gate (Figure 5). V PNH(CONDUCTION) = ILOAD2RDS(ON)NH OUT VIN PNH(TOTAL) = PNH(SWITCHING) + PNH(CONDUCTION) V PNL = ILOAD2RDS(ON)NL 1- OUT VIN To reduce EMI caused by switching noise, add a 0.1F ceramic capacitor from the high-side switch drain to the low-side switch source or add resistors (max 47) in series with DL and DH to increase the switches' turn-on and turn-off times (Figure 5). The minimum load current should exceed the high-side MOSFET's maximum leakage current over temperature if fault conditions are expected.
MAX1964 MAX1965
BST RGATE (OPTIONAL) NH CBST RGATE (OPTIONAL) NL L
DH LX TO VL DH GND
Figure 5. Reducing the Switching EMI
Input Capacitor The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit's switching. The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents defined by the following equation:
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers
IRMS = ILOAD VOUT (VIN - VOUT ) VIN high quality low-ESR aluminum-electrolytic, tantalum, polymer, or ceramic filter capacitors are required to minimize output ripple. Best results at reasonable cost are typically achieved with an aluminum-electrolytic capacitor in the 470F range, in parallel with a 0.1F ceramic capacitor. Since the MAX1964/MAX1965 use a current-mode control scheme, the output capacitor forms a pole that affects circuit stability (see Compensation Design). Furthermore, the output capacitor's ESR also forms a zero. The MAX1964/MAX1965's response to a load transient depends on the selected output capacitor. After a load transient, the output instantly changes by ESR x ILOAD. Before the controller can respond, the output will sag further depending on the inductor and output capacitor values. After a short period of time (see Typical Operating Characteristics), the controller responds by regulating the output voltage back to its nominal state. For applications that have strict transient requirements, low-ESR high-capacitance electrolytic capacitors are recommended to minimize the transient voltage swing. Do not exceed the capacitor's voltage or ripple-current ratings.
MAX1964/MAX1965
I RMS has a maximum value when the input voltage equals twice the output voltage (V IN = 2V OUT ), so IRMS(MAX) = ILOAD/2. For most applications, nontantalum capacitors (ceramic, aluminum, polymer, or OSCON) are preferred due to their robustness with high inrush currents typical of systems with low impedance inputs. Additionally, two (or more) smaller value lowESR capacitors can be connected in parallel for lower cost. Choose an input capacitor that exhibits less than +10C temperature rise at the RMS input current for optimal circuit long-term reliability. Output Capacitor The key selection parameters for the output capacitor are the actual capacitance value, the equivalent series resistance (ESR), and voltage-rating requirements which affect the overall stability, output ripple voltage, and transient response. The output ripple has two components: variations in the charge stored in the output capacitor, and the voltage drop across the capacitor's equivalent series resistance (ESR) caused by the current into and out of the capacitor. VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) The output voltage ripple as a consequence of the ESR and output capacitance is: VRIPPLE(ESR) = IP-PESR VRIPPLE(C) = IP-P 8COUT SW
Compensation Design
The MAX1964/MAX1965 controllers use an internal transconductance error amplifier whose output allows compensation of the control loop. Connect a series resistor and capacitor between COMP and GND to form a pole-zero pair, and connect a second parallel capacitor between COMP and GND to form another pole. The external inductor, high-side MOSFET, output capacitor, compensation resistor, and compensation capacitors determine the loop stability. The inductor and output capacitor are chosen based on performance, size, and cost, while the compensation resistor and capacitors are selected to optimize control-loop stability. The component values shown in the Standard Application Circuit (Figures 1 and 6) yield stable operation over a broad range of input-to-output voltages. The controller uses a current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor, so the MAX1964/MAX1965 use the voltage across the highside MOSFET's on-resistance (RDS(ON)) to sense the inductor current. Using the current-sense amplifier's output signal and the amplified feedback voltage, the control loop determines the peak inductor current by:
V -V V IP-P = IN OUT OUT SW L VIN where Ip-p is the peak-to-peak inductor current (see Inductor Selection section). These equations are suitable for initial capacitor selection, but final values should be set by testing a prototype or evaluation circuit. As a general rule, a smaller ripple current results in less output ripple. Since the inductor ripple current is a factor of the inductor value and input voltage, the output voltage ripple decreases with larger inductance, but increases with lower input voltages. With low-cost aluminum electrolytic capacitors, the ESR-induced ripple can be larger than that caused by the charge into and out of the capacitor. Consequently,
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
IPEAK = VOUT VREF A VEA VOUT(NOMINAL)RDS(ON)A VCS fPOLE(OUT) = ILOAD(MAX) 1 = 2COUTRLOAD 2COUT VOUT
where VREF = 1.24V, AVCS is the current-sense amplifier's gain (4.9 typ), AVEA is the DC gain of the transconductance error amplifier (2000 typ) set by its DC output resistance, and VOUT(NOMINAL) is the output voltage set by the feedback resistive-divider (internal or external). Since the output voltage is a function of the load current and load resistance, the total DC loop gain (AV(DC)) is approximately: I VREFRLOADA VEA A V(DC) PEAK ILOAD VOUT(NOMINAL)RDS(ON)A VCS 400 x VREFRLOAD VOUT(NOMINAL)RDS(ON)
4) The series compensation resistor and capacitor provide a zero which can be used to cancel the second pole in order to ensure stability: RCOMP 1 2CCOMP1fPOLE(OUT)
5) For most applications using electrolytic capacitors, the output capacitor's ESR forms a second zero that occurs before crossover. Applications using low-ESR capacitors (e.g., polymer, OS-CON) may have ESR zeros that occur after crossover. Therefore, verify the frequency of the output capacitor's ESR zero: fZERO(ESR) 1 2COUTRESR
The first compensation capacitor (CCOMP1) creates the dominant pole. Due to the current-mode control scheme, the output capacitor also creates a pole in the system which is a function of the load resistance. As the load resistance increases, the frequency of the output capacitor's pole decreases. However, the DC loop gain increases with larger load resistance, so the unitygain bandwidth remains fixed. Additionally, the compensation resistor and the output capacitor's ESR both generate zeros which must be canceled out by corresponding poles. Therefore, in order to achieve stable operation, use the following procedure to properly compensate the system: 1) The crossover frequency (the frequency at which unity gain occurs) must be less than 1/5th the switching frequency: f fC SW 5 2) Determine the series compensation capacitor (CCOMP1) required to set the desired crossover frequency: CCOMP1 1 gm AV(DC) 2 2000fC
6) Finally, if the output capacitor's ESR zero occurs before crossover, add the parallel compensation capacitor (CCOMP2) to form a third pole to cancel this second zero: CCOMP2
(2RCOMPCCOMP1fZERO(ESR) - 1) (fZERO(ESR) - fPOLE(OUT) )
CCOMP1fPOLE(OUT)
CCOMP1
For example, the MAX1964 Standard Application Circuit shown in Figure 1 requires a 5V output that supports up to 2A. Using the above compensation guidelines, we can determine the proper component values: * First, select the crossover frequency to be 1/5th the 200kHz switching frequency. * Next, determine the total DC loop gain (AV(DC)) so you can calculate the series compensation capacitance (CCOMP1). Since the applications circuit uses the International Rectifier IRF7101 with an RDS(ON) of 100m, the DC loop gain approximately equals 2480 and CCOMP1 must be approximately 490pF. Select the closest standard capacitor value of 470pF. Determine the location of the output pole (fPOLE(OUT)). With a 5V output supplying 2A and a 1000F electrolytic capacitor, the output pole occurs at 64Hz.
where the error amplifier's transconductance (gm) is 100S (see Electrical Characteristics) and AV(DC) is the total DC loop gain defined above. 3) Before crossover occurs, the output capacitor and the load resistor generate a second pole:
*
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers
* With the output pole's frequency and series compensation capacitor values, the required series resistance can be determined. Based on the above equation, select RCOMP = 5.1M. Now we must determine if the selected output capacitor's ESR generates a second zero before crossover--the circuit shown in Figure 1 uses a 1000F 10V Sanyo CZ-series electrolytic capacitor with an ESR rating of 0.2, so the zero occurs at 800Hz. Since crossover occurs at 40kHz, add the second parallel compensation capacitor. Finally, the second compensation capacitor value must be approximately 43pF. Select the closest standard capacitor value of 47pF. can source at least 25mA. Typically, the OUT pin is connected to the step-down converter's output. However, if the step-down converter's output voltage is set higher than 5V, OUT must be connected to one of the positive linear regulators with an output voltage between 2V and 5V. Transistor Selection The pass transistors must meet specifications for current gain (hFE), input capacitance, collector-emitter saturation voltage, and power dissipation. The transistor's current gain limits the guaranteed maximum output current to: V ILOAD(MAX) = IDRV - BE hFE(MIN) RBE where IDRV is the minimum 10mA base drive current and R BE (220) is the pullup resistor connected between the transistor's base and emitter. Furthermore, the transistor's current gain increases the linear regulator's DC loop gain (see Stability Requirements), so excessive gain will destabilize the output. Therefore, transistors with current gain over 100 at the maximum output current, such as Darlington transistors, are not recommended. The transistor's input capacitance and input resistance also create a second pole, which could be low enough to destabilize the output when heavily loaded. The transistor's saturation voltage at the maximum output current determines the minimum input-to-output voltage differential that the linear regulator will support. Alternatively, the package's power dissipation could limit the useable maximum input-to-output voltage differential. The maximum power dissipation capability of the transistor's package and mounting must exceed the actual power dissipation in the device. The power dissipated equals the maximum load current times the maximum input-to-output voltage differential: P = ILOAD(MAX)(VLDOIN - VOUT) = ILOAD(MAX) VCE Stability Requirements The MAX1964/MAX1965 linear regulators use an internal transconductance amplifier to drive an external pass transistor. The transconductance amplifier, pass transistor's specifications, the base-emitter resistor, and the output capacitor determine the loop stability. If the output capacitor and pass transistor are not properly selected, the linear regulator will be unstable. The transconductance amplifier regulates the output voltage by controlling the pass transistor's base current. Since the output voltage is a function of the load
21
MAX1964/MAX1965
*
*
Boost-Supply Diode A signal diode, such as the 1N4148, works well in most applications. If the input voltage goes below 6V, use a small 20mA Schottky diode for slightly improved efficiency and dropout characteristics. Do not use large power diodes, such as the 1N5817 or 1N4001, since high junction capacitance can charge up VL to excessive voltages.
Linear Regulator Controllers
Positive Output Voltage Selection The MAX1964/MAX1965's positive linear regulator output voltages are set by connecting a voltage divider from the output to FB_ to GND (Figure 6). Select R4 in the 1k to 50k range. Calculate R3 with the following equation: V R3 = R4 OUT - 1 VFB where VFB = 1.24V and VOUT may range from 1.24V to 30V. Negative Output Voltage Selection (MAX1965) The MAX1965's negative output voltage is set by connecting a voltage divider from the output to FB5 to a positive voltage reference (Figure 6). Select R6 in the 1k to 50k range. Calculate R5 with the following equation: V R5 = R6 OUT VREF where VREF is the positive reference voltage used and VOUT may be set between 0 and -20V. If the negative regulator is used, the OUT pin must be connected to a voltage supply between 2V and 5V that
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
D1 CENTRAL CMPSH-3 INPUT 9V TO 18V CIN 470F
IN C1 1F
BST DH
RGATE(NH) 10 NH CBST 0.1F RGATE(NL) 10
FAIRCHILD FDS6912A T1 NP = 1 VOUT1 3.3V AT 1.4A COUT 470F 10V SANYO (MV-AX SERIES)
VL C2 1F
LX
ILIM RPOK 100k
DL
NL
MAX1965
OUT GND
TO LOGIC
POK FB CBE2 2200pF RBE2 220 R1 10k R2 10k C3 1F
RCOMP 412k COMP CCOMP1 1500pF T1 NS(NEG) = 2 D3 NIHON EC10QS10 C10 47F C11 1F CCOMP2 68pF B2
Q1 TIP30
VOUT2 2.5V AT 200mA C4 10F
FB2
CBE3 2200pF RBE3 220 R3 1.3k R4 3.0k
C5 1F
B3
Q2 TIP32
VOUT3 1.8V AT 500mA C6 10F
NS(POS) = 1
T1
FB3 CBE5 2200pF Q4 TIP29 VOUT5 -5V AT 50mA RBE5 220 R8 30k C5 10F B3 B5 FB5
D2 NIHON EP05Q03L C8 47F
CBE4 4700pF RBE4 220 R5 30k R6 10k
C7 1F
Q3 2N3905
VOUT3 5V AT 100mA POWER GROUND C9 10F ANALOG GROUND NOTE: ALL T1 TRANSFORMER WINDINGS ARE ON THE SAME CORE
FB3 CONNECT TO VOUT2
R7 15k
Figure 6. MAX1965 Application Circuit
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current and load resistance, the total DC loop gain (AV(LDO)) is approximately: 5.5 IBIAShFE A V(LDO) 1 + VREF VT ILOAD where VT is 26mV, and IBIAS is the current through the base-to-emitter resistor (RBE). This bias resistor is typically 220, providing approximately 3.2mA of bias current. The output capacitor creates the dominant pole. However, the pass transistor's input capacitance creates a second pole in the system. Additionally, the output capacitor's ESR generate a zero, which may be used to cancel the second pole if necessary. Therefore, in order to achieve stable operation, use the following equations to verify that the linear regulator is properly compensated: 1) First, determine the dominant pole set by the linear regulator's output capacitor and the load resistor: POLE(CLDO) = ILOAD(MAX) 1 = 2CLDORLOAD 2CLDOVLDO
MAX1964/MAX1965
POLE(FB)
1 COUTRESR
Do not use output capacitors with more than 200m of ESR. Typically, more output capacitance provides the best solution, since this also reduces the output voltage drop immediately after a load transient. Linear Regulator Output Capacitors Connect at least 1F capacitor between the linear regulator's output and ground, as close to the MAX1964/ MAX1965 and external pass transistors as possible. Depending on the selected pass transistor, larger capacitor values may be required for stability (see Stability Requirements). Furthermore, the output capacitor's equivalent series resistance (ESR) affects stability, providing a zero that may be necessary to cancel the second pole. Use output capacitors with an ESR less than 200m to ensure stability and optimum transient response. Once the minimum capacitor value for stability is determined, verify that the linear regulator's output does not contain excessive noise. Although adequate for stability, small capacitor values may provide too much bandwidth, making the linear regulator sensitive to noise. Larger capacitor values reduce the bandwidth, thereby reducing the regulator's noise sensitivity. For the negative linear regulator, if noise on the ground reference causes the design to be marginally stable, bypass the negative output back to its reference voltage (VREF, Figure 7). This technique reduces the differential noise on the output. Base-Drive Noise Reduction The high-impedance base driver is susceptible to system noise, especially when the linear regulator is lightly loaded. Capacitively coupled switching noise or inductively coupled EMI onto the base drive causes fluctuations in the base current, which appear as noise on the linear regulator's output. Keep the base-drive traces away from the step-down converter and as short as possible to minimize noise coupling. Resistors in series with the gate drivers (DH and DL) reduce the LX switching noise generated by the step-down converter (Figure 5). Additionally, a bypass capacitor may be placed across the base-to-emitter resistor (Figure 7). This bypass capacitor, in addition to the transistor's input capacitance, could bring in a second pole that will destabilize the linear regulator (see Stability Requirements). Therefore, the stability requirements determine the maximum base-to-emitter capacitance:
unity-gain crossover = AV(LDO) POLE(CLDO) 2) Next, determine the second pole set by the base-toemitter capacitance (including the transistor's input capacitance), the transistor's input resistance, and the base-to-emitter pullup resistor: POLE(CBE) =
2CBE RBE RIN(BJT)
+ VThFE RI = BE LOAD 2CBERBE VThFE
(
1
)
3) A third pole is set by the linear regulator's feedback resistance and the capacitance between FB_ and GND (including 20pF stray capacitance). POLE(FB) = 1
2CFB R1 R2
(
)
4) If the second and third pole occur well after unitygain crossover, the linear regulator will remain stable: POLE(FB) and POLE(CBE) > 2POLE(CLDO) AV(LDO) However, if the ESR zero occurs before unity-gain crossover, cancel the zero with fPOLE(FB) by changing circuit components such that:
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
VSUP
MAX1964 MAX1965
CBE B_ R1
RBE QPASS
CBYP
VPOS FB_ R2 CLDO
a) POSITIVE OUTPUT VOLTAGE
R4 VREF BF5 R3 VNEG B5 CBE RBE VSUP b) NEGATIVE OUTPUT VOLTAGE (MAX1965 ONLY) CBYP QPASS CNEG
MAX1965
Figure 7. Base-Drive Noise Reduction
CBE
RBEILOAD + VThFE - CIN(Q) 2 POLE(CBE) RBEVThFE 1
where CIN(Q) is the transistor's input capacitance, and fPOLE(CBE) is the second pole required for stability. Transformer Selection In systems where the step-down controller's output is not the highest voltage, a transformer may be used to provide additional post-regulated, high-voltage outputs. The transformer generates unregulated, high-voltage supplies which power the positive and negative linear regulators. These unregulated supply voltages are dependent on the transformer's turns ratio - number of secondary turns (NS) divided by the number of primary turns (NP). So the transformer must be selected to provide supply voltages high enough to keep the pass transistors from saturating. For positive output voltages, connect the transformer as shown in Figure 6 where the minimum turns ratio (NPOS = NS(POS)/NP) is determined by: VLDO(POS) + VSAT + VDIODE NPOS -1 VOUT
where VSAT is the pass transistor's saturation voltage under full load. For negative output voltages (MAX1965 only), connect the transformer as shown in Figure 6 where the minimum turns ratio (NNEG = NS(NEG)/NP) is determined by: VLDO(NEG) + VSAT + VDIODE NNEG VOUT Since power transfer occurs when the low-side MOSFET is on (DL = high), the transformer cannot support heavy loads with high duty cycles.
Snubber Design
The MAX1964/MAX1965 use current-mode control schemes that sense the current across the high-side MOSFET (NH). Immediately after the high-side MOSFET turns on, the MAX1964/MAX1965 use a 60ns currentsense blanking period to minimize noise sensitivity. However, when the MOSFET turns on, the transformer's secondary inductance and the diode's parasitic capacitance form a resonant circuit that causes ringing. Reflected back through the transformer to the primary side, these oscillations appear across the high-side MOSFET may last longer than the blanking period. As
24
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers
shown in Figure 8, a series RC snubber circuit at the diode increases the damping factor, allowing the ringing to settle quickly. Applications with multiple transformer windings require only one snubber circuit on the highest output voltage. The diode's parasitic capacitance can be estimated using the diode's reverse voltage rating (VRRM), current capability (I O ), and recovery time (t RR ). A rough approximation is: I xt CDIODE = 0 RR VRRM For the EC10QS10 Nihon diode used in Figure 8, the capacitance is roughly 15pF. The output snubber only needs to dampen the ringing, so the initial turn-on spike that occurs during the blanking period is still present. A 100pF capacitor works well in most applications. Larger capacitance values require more charge, thereby increasing the power dissipation. The snubber's time constant (tSNUB) must be smaller than the 60ns blanking time. A typical RC time constant of approximately 30ns was chosen for Figure 8: t 30ns RSNUB = SNUB = CSNUB CSNUB Minimum Load Requirements (Linear Regulators) Under no-load conditions, leakage currents from the pass transistors supply the output capacitor, even when the transistor is off. Generally, this is not a problem since the feedback resistors' current drain the excess charge. However, charge may build up on the output capacitor over temperature, making VLDO rise above its set point. Care must be taken to ensure that the feedback resistors' current exceeds the pass transistor's leakage current over the entire temperature range. 2) Mount the MAX1964/MAX1965 adjacent to the switching MOSFETs in order to keep IN-LX currentsense lines, LX-GND current-limit sense lines, and the driver lines (DL and DH) short and wide. The current-sense amplifier inputs are connected between IN and LX, so these pins must be connected as close as possible to the high-side MOSFET. The current-limit comparator inputs are connected between LX and GND, but accuracy is not as important, so give priority to the high-side MOSFET connections. The IN, LX, and GND connections to the MOSFETs must be made using Kelvin sense connections to guarantee current-sense and current-limit accuracy. 3) Group the gate-drive components (BST diode and capacitor, IN bypass capacitor) together near the MAX1964/MAX1965. 4) All analog grounding must be done to a separate solid copper ground plane, which connects to the MAX1964/MAX1965 at the GND pin. This includes the VL bypass capacitor, feedback resistors, compensation components (R COMP , C COMP ), and adjustable current-limit threshold resistors connected to ILIM. 5) Ensure all feedback connections are short and direct. Place the feedback resistors as close to the MAX1964/MAX1965 as possible. 6) When trade-offs in trace lengths must be made, it's preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and low-side MOSFET. 7) Route high-speed switching nodes away from sensitive analog areas (B_, FB_, COMP, ILIM).
MAX1964/MAX1965
Regulating High Voltage
The linear regulator controllers can be configured to regulate high output voltages by adding a cascode transistor to buffer the base-drive output. For example, to generate an output voltage between 30V and 60V, add a 2N5550 high-voltage NPN transistor as shown in Figure 9A where VBIAS is a DC voltage between 3V and 20V that can source at least 1mA. RDROP protects the cascode transistor by decreasing the voltage across the transistor when the pass transistor saturates. Similarly, to regulate a negative output voltage between -20V and -120V, add a 2N5401 high-voltage PNP transistor as shown in Figure 9B.
Applications Information
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. Follow these guidelines for good PC board layout: 1) Place the power components first, with ground terminals adjacent (NL source, CIN, COUT). If possible, make all these connections on the top layer with wide, copper-filled areas. Keep these high-current paths short, especially at ground terminals.
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25
Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
D1 CENTRAL CMPSH-3 INPUT 9V TO 18V CIN 470F
IN C1 1F
BST DH
RGATE(NH) 10 NH CBST 0.1F RGATE(NL) 10
FAIRCHILD FDS6912A T1 1 COUT 470F VOUT1 3.3V AT 1A
VL C2 1F ILIM RPOK 100k
LX
DL
NL 1
MAX1964
OUT GND D2 NIHON EP05Q03L CBE2 4700pF RBE2 220 R3 30k R4 10k C3 10F COUT 470F
T1
TO LOGIC
POK
FB
B2
Q1 2N3905
VOUT2 5V AT 100mA C5 10F
2 T1 D3 NIHON EC10QS10 C6 10F C7 470F RSNUB 300
RCOMP 200k COMP CCOMP 8.2nF
FB2
C9 10nF
CBE3 2200pF RBE3 220 R5 86.6k R6 10k
B3 R7 470 FB3
Q2 TIP30
VOUT3 12V AT 100mA C8 10F
CSNUB 100pF
POWER GROUND
ANALOG GROUND
Figure 8. MAX1964 High-Voltage Application Requires Snubber Circuit
Output Filtering for Analog Circuits
Some applications need to generate analog and power outputs at the same voltage. By adding an LC filter to filter the noise present on an analog output (Figure 10), one output voltage can provide both analog and power outputs. The LC filter provides approximately 40dB/decade of attenuation. Select the LC corner frequency (1/2 LC) to provide desired attenuation. For stable operation, the filter inductor (LFILTER) and output
26
filter capacitor (C FILTER) used to generate the filter must be selected to provide an overdamped response to output transients:
(RDCR + RESR )2 CFILTER
4LFILTER
1
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
VBIAS CDROP RBE B_ QCASCODE QPASS RDROP VPOS FB_ R1 CPOS R2 a) POSITIVE OUTPUT VOLTAGE WITH CASCODED BASE DRIVE VSUP CBYP
MAX1964 MAX1965
R4 VREF FB5 R3 VNEG B5 QCASCODE RDROP QPASS RBE CDROP VSUP b) NEGATIVE OUTPUT VOLTAGE (MAX1965 ONLY) WITH CASCODED BASE DRIVE CBYP CNEG
MAX1965
Figure 9. High-Voltage Linear Regulation
where the RDCR is the inductor's DC resistance and R ESR is the output filter capacitor's effective series resistance (ESR). Inductors with high DC resistance will provide poor load regulation but allow the use of smaller filter capacitors: VOUT(FILTER) = VOUT(NOMINAL) - RDCRIOUT Therefore, power chokes are ideal for these applications due to their high inductance values, high saturation current ratings, and low resistance.
Chip Information
TRANSISTOR COUNT: 1617 PROCESS: BiCMOS
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27
Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
D1 CIN INPUT 9V TO 18V
IN C1
MAX1964 MAX1965 BST
DH CBST NH L COUT LFILTER POWER OUTPUT
VL C2 ILIM RPOK TO LOGIC RCOMP POK COMP CCOMP1 CCOMP2
LX DL NL
OUT GND FB POWER GROUND
ANALOG OUTPUT CFILTER
ANALOG GROUND
Figure 10. Filtered Output for Analog Circuits
Table 1. Component Suppliers
SUPPLIER INDUCTORS & TRANSFORMERS Coilcraft Coiltronics ICE Components Sumida USA Toko CAPACITORS AVX Kemet Panasonic Sanyo Taiyo Yuden DIODES Central Semiconductor International Rectifier Nihon On Semiconductor Zetex 516-435-1110 310-322-3331 847-843-7500 602-303-5454 516-543-7100 516-435-1824 310-322-3332 847-843-2798 602-994-6430 516-864-7630 www.centralsemi.com www.irf.com www.niec.co.jp www.onsemi.com www.zetex.com 803-946-0690 408-986-0424 847-468-5624 619-661-6835 408-573-4150 803-626-3123 408-986-1442 847-468-5815 619-661-1055 408-573-4159 www.avxcorp.com www.kemet.com www.panasonic.com www.secc.co.jp www.t-yuden.com 847-639-6400 561-241-7876 800-729-2099 847-956-0666 847-297-0070 847-639-1469 561-241-9339 800-729-2099 847-956-0702 847-699-1194 www.coilcraft.com www.coiltronics.com www.icecomponents.com www.sumida.com www.tokoam.com PHONE FAX WEBSITE
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers
Typical Operating Circuit
INPUT
MAX1964/MAX1965
IN
BST DH
VL
LX
MAIN OUTPUT
ILIM
DL
MAX1964 MAX1965 OUT
GND POK FB
COMP
B2 OUT #2 FB2
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Tracking/Sequencing Triple/Quintuple Power-Supply Controllers MAX1964/MAX1965
Package Information
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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